PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 60
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PIC16F785-I/P
Manufacturer Part Number
PIC16F785-I/P
Description
MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F785-IP.pdf
(184 pages)
Specifications of PIC16F785-I/P
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
17
Memory Type
Flash
Number Of Bits
8
Package Type
20-pin PDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16F785/HV785
8.1
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC5/CCP1. An event is defined as one of the
following and is configured by CCP1CON<3:0>:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the interrupt request flag bit
CCP1IF (PIR1<5>) is set. The interrupt flag must be
cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
8.1.1
In Capture mode, the RC5/CCP1 pin should be config-
ured as an input by setting the TRISC<5> bit.
FIGURE 8-1:
8.1.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
8.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<5>) clear to avoid false interrupts and
should clear the flag bit CCP1IF (PIR1<5>) following
any such change in Operating mode.
DS41249D-page 58
RC5/CCP1
pin
Note:
Capture Mode
Edge Detect
Q’s
CCP1 PIN CONFIGURATION
If the RC5/CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
Prescaler
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
1, 4, 16
and
CCP1CON<3:0>
Set Flag bit CCP1IF
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
(PIR1<5>)
Capture
Enable
CCPR1H
TMR1H
CCPR1L
TMR1L
Preliminary
8.1.4
There are four prescaler settings specified by bits
CCP1M<3:0> (CCP1CON<3:0>). Whenever the CCP
module is turned off, or the CCP module is not in Cap-
ture mode, the prescaler counter is cleared. Any Reset
will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 8-1:
8.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC5/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF (PIR1<5>) is set.
FIGURE 8-2:
CLRF
MOVLW
MOVWF
RC5/CCP1
Pin
Special Event Trigger will:
• clear TMR1H and TMR1L registers
• NOT set interrupt flag bit TMR1F (PIR1<0>)
• set the GO/DONE bit (ADCON0<1>)
Output Enable
TRISC<5>
Compare Mode
CCP1CON
NEW_CAPT_PS ;Load the W reg with
CCP1CON
CCP PRESCALER
Q
Special Event Trigger
CCP1CON<3:0>
R
S
Mode Select
Output
CHANGING BETWEEN
CAPTURE PRESCALERS
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
;Turn CCP module off
; the new prescaler
; move value and CCP ON
;Load CCP1CON with this
; value
© 2006 Microchip Technology Inc.
Set Flag bit CCP1IF
4
(PIR1<5>)
Match
CCPR1H CCPR1L
TMR1H
Comparator
TMR1L
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