PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 61

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

8.2.1
The user must configure the RC5/CCP1 pin as an
output by clearing the TRISC<5> bit.
8.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the RC5/CCP1 pin is not
affected. The CCP1IF (PIR1<5>) bit is set, causing a
CCP interrupt (if enabled). See Register 8-1.
TABLE 8-2:
© 2006 Microchip Technology Inc.
0Bh
8Bh
0Ch
0Eh
0Fh
10h
11Bh
13h
14h
15h
87h,
187h
8Ch
Legend:
Addr
Note:
INTCON
PIR1
TMR1L
TMR1H
T1CON
CM2CON1 MC1OUT MC2OUT
CCPR1L
CCPR1H
CCP1CON
TRISC
PIE1
Name
module.
CCP1 PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC5/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare or Timer1
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
T1GINV
TRISC7
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Bit 7
EEIF
EEIE
GIE
—
TMR1GE
TRISC6
PEIE
ADIF
ADIE
Bit 6
—
T1CKPS1
CCP1IF
TRISC5
CCP1IE
DC1B1
Bit 5
T0IE
—
T1CKPS0
TRISC4
DC1B0
INTE
C2IE
Bit 4
C2IF
—
Preliminary
T1OSCEN
CCP1M3
TRISC3
RAIE
Bit 3
C1IF
C1IE
—
8.2.4
In this mode (CCP1M<3:0> = 1011), an internal
hardware trigger is generated, which may be used to
initiate an action. See Register 8-1.
The special event trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and CCPR1H, CCPR1L register
pair. The TMR1H, TMR1L register pair is not reset until
the next rising edge of the TMR1 clock. This allows the
CCPR1H, CCPR1L register pair to effectively provide a
16-bit programmable period register for Timer1. The
special event trigger output also starts an A/D
conversion provided that the A/D module is enabled.
CCP1M2
Note 1: The special event trigger from the CCP
T1SYNC
TRISC2
OSFIE
OSFIF
Bit 2
T0IF
—
PIC16F785/HV785
2: Removing the match condition by chang-
SPECIAL EVENT TRIGGER
TMR1CS
CCP1M1
TMR2IF
TMR2IE
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
ing the contents of the CCPR1H and
CCPR1L register pair between the clock
edge that generates the special event
trigger and the clock edge that generates
the TMR1 Reset, will preclude the Reset
from occurring.
TRISC1
T1GSS
Bit 1
INTF
TMR1ON
C2SYNC
CCP1M0
TMR1IF
TMR1IE
TRISC0
RAIF
Bit 0
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
00-- --10
xxxx xxxx
xxxx xxxx
--00 0000
--11 1111
0000 0000
POR, BOR
Value on:
DS41249D-page 59
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
00-- --10
uuuu uuuu
uuuu uuuu
--00 0000
--11 1111
0000 0000
Value on
all other
Resets