SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 341

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

PNX1300/01/02/11 Data Book
fdivflags
SYNTAX
FUNCTION
DESCRIPTION
rsrc1÷rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE
single-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same
format as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation.
Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted
before computing the quotient, and the IFZ bit in the result is set. If the quotient would be denormalized, the OFZ bit in
the result is set.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
A-43
r30 = 0x7f7fffff (3.402823466e+38),
r40 = 0x3f800000 (1.0)
r10 = 0,
r50 = 0x7f7fffff (3.402823466e+38)
r60 = 0x3e000000 (0.125)
r20 = 1,
r50 = 0x7f7fffff (3.402823466e+38)
r60 = 0x3e000000 (0.125)
r70 = 0x40400000 (3.0),
r80 = 0x00400000 (5.877471754e–39)
r85 = 0x7f800000 (+INF),
r86 = 0xff800000 (–INF)
The
The
[ IF rguard ] fdivflags rsrc1 rsrc2 → rdest
if rguard then
fdivflags
rdest ← ieee_flags((float)rsrc1 / (float)rsrc2)
fdivflags
31
0
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation computes the IEEE exceptions that would result from computing the quotient
PRELIMINARY SPECIFICATION
fdivflags r30 r40 → r100
IF r10 fdivflags r50 r60 → r110
IF r20 fdivflags r50 r60 → r111
fdivflags r70 r80 → r112
fdivflags r85 r86 → r113
IEEE status flags from floating-point divide
Operation
7
0
OFZ
6
IFZ
5
INV
4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Recovery
Issue slots
fdiv faddflags readpcsw
r100 ← 0
no change, since guard is false
r111 ← 0xa (OVF INX)
r112 ← 0x21 (IFZ DBZ)
r113 ← 0x10 (INV)
OVF
3
Philips Semiconductors
UNF
ATTRIBUTES
2
SEE ALSO
Result
INX
1
DBZ
0
ftough
109
No
17
16
—
2
2