SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 71

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

Philips Semiconductors
Note that this comparison works for all addresses re-
gardless of the aperture to which they belong. When the
value of the DC bits is ‘2’ or ‘3’, any data value from load
operations (if the BL bit is set) and/or store operations (if
the BS bit is set) issued by the PNX1300 CPU is com-
pared against the value in the BDATAVAL register. Only
the bits for which the corresponding BDATAMASK regis-
ter bits are set to ‘1’ will be used in the comparison. The
DVC bit in the breakpoint control register determines
whether the data value needs to be equal or not equal to
the comparison value. A successful comparison occurs
when either of the following are true:
• DVC = ‘0’ and (data & BDATAMASK) = (BDATAVAL
• DVC = ‘1’ and (data & BDATAMASK) != (BDATAVAL
& BDATAMASK).
& BDATAMASK).
Note: use a nonzero datamask or the result is undefined.
When a successful comparison has taken place, a data
breakpoint event is generated, which can be used as a
clock input to a timer. After counting the set number of
data breakpoint events, the timer will generate an inter-
rupt request.
When the value of the DC bits is ‘3’, a data breakpoint
event is generated if and only if a successful comparison
occurs on both address and data simultaneously.
Note that up to two data breakpoint events can occur per
clock cycle, due to the dual load/store capability of the
CPU and data cache.
PRELIMINARY SPECIFICATION
DSPCPU Architecture
3-15