SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 427

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

PNX1300/01/02/11 Data Book
ld32
SYNTAX
FUNCTION
DESCRIPTION
argument. (Note: pseudo operations cannot be used in assembly source files.)
rdest. If the memory address contained in rsrc1 is not a multiple of 4, the result of
will be raised. This load operation is performed as little-endian or big-endian depending on the current setting of the
bytesex bit in the PCSW.
memory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
EXAMPLES
A-129
r10 = 0xd00,
[0xd00] = 0x84, [0xd01] = 0x33,
[0xd02] = 0x22, [0xd03] = 0x11
r30 = 0, r20 = 0xd04,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r40 = 1, r20 = 0xd04,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r50 = 0xd01
The
The
The
The
[ IF rguard ] ld32 rsrc1 → rdest
if rguard then {
}
if PCSW.bytesex = LITTLE_ENDIAN then
else
rdest<7:0> ← mem[rsrc1 + (3 ⊕ bs)]
rdest<15:8> ← mem[rsrc1 + (2 ⊕ bs)]
rdest<23:16> ← mem[rsrc1 + (1 ⊕ bs)]
rdest<31:24> ← mem[rsrc1 + (0 ⊕ bs)]
ld32
ld32
bs ← 3
bs ← 0
ld32
ld32
Initial Values
operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bit
operation loads the 32-bit memory value from the address contained in rsrc1 and stores the result in
ld32
operation is a pseudo operation transformed by the scheduler into an
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
has no side effects whatever.
PRELIMINARY SPECIFICATION
ld32 r10 → r60
IF r30 ld32 r20 → r70
IF r40 ld32 r20 → r80
ld32 r50 → r90
Operation
r60 ← 0x84332211
no change, since guard is false
r80 ← 0x48665544
r90 undefined, since 0xd01 is not a multiple of 4
ld32
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ld32d ld32r ld32x st32
is undefined but no exception
Philips Semiconductors
pseudo-op for ld32d(0)
ld32d(0)
st32d h_st32d
Result
ATTRIBUTES
SEE ALSO
32-bit load
with the same
ld32
dmem
4, 5
No
—
7
1
3
.