SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 444

IC DIGITAL VIDEO DECODER 100LQFP

SAA7115HL/V1,518

Manufacturer Part Number
SAA7115HL/V1,518
Description
IC DIGITAL VIDEO DECODER 100LQFP
Manufacturer
NXP Semiconductors
Type
Video Decoderr
Datasheets

Specifications of SAA7115HL/V1,518

Package / Case
100-LQFP
Applications
Set-Top Boxes
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply, Analog
-
Voltage - Supply, Digital
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935270666518
SAA7115HLBE-T
SAA7115HLBE-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAA7115HL/V1,518
Manufacturer:
Sigma Designs Inc
Quantity:
10 000
Philips Semiconductors
prefetch with 32-bit scaled index
SYNTAX
[ IF rguard ] pref32x rsrc1 rsrc2
FUNCTION
DESCRIPTION
(4 x rscr2)) & cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to be
executed. The prefetch unit will not execute this operation when the data to be prefetched is already in the data cache.
A pref32x operation will not be executed when the cache is already occupied with 2 cache misses, when the operation
is issued.
execution of the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is not
executed..
EXAMPLES
NOTE: This operation may only be supported in TM-1000, TM-1100, TM-1300 and
PNX1300/01/02/11. It is not guaranteed to be available in future generations of Trimedia
products.
r10 = 0xabcd, r12 = 0xd
cache_block_size = 0x40
r10 = 0xabcd, r11 = 0, r12=0xd,
cache_block_size = 0x40
r10 = 0xabff, r11 = 1, r12 =0x1,
cache_block_size = 0x40
The pref32x operation loads the one full cache block size of memory value from the address computed by ((rsrc1+
The pref32x operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
if rguard then {
}
cache_block_mask = ~(cache_block_size - 1)
data_cache <- mem[(rsrc1 + (4 x rscr2)) & cache_block_mask]
Initial Values
pref32x r10 r12
IF r11 pref32x r10 r12
IF r11 pref32x r10 r12
Operation
PRELIMINARY SPECIFICATION
Loads a cache line for the address space from
0xac00 to 0x0xac3f from the main memory. If the
data is already in the cache, the operation is not exe-
cuted.
since guard is false, pref32x operation is not exe-
cuted
Loads a cache line for the address space from
0xac00 to 0x0xac3f from the main memory. If the
data is already in the cache, the operation is not exe-
cuted.
PNX1300/01/02/11 DSPCPU Operations
pref16x prefd prefr allocd
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
Result
allocr allocx
ATTRIBUTES
SEE ALSO
pref32x
dmemspec
212
No
2
5
-
-
A-146

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