SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 534

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

igeq
igeqi
igtr
igtri
iimm
iis
ijmpf
ijmpi
ijmpt
ild16
ild16d
ild16r
ild16x
ild8
ild8d
ild8r
ileq
ileqi
iles
ilesi
image
Image co-processor
image co-processor
image overlay 14-1, 14-5,
image overlay formats
image processing
IMASK
imax
imin
imul
imulm
ineg
ineq
ineqi
initialization
initialization,cache
inonzero
input format
Index-8
A B C
8-1
A-98
A-113
A-108
A-111
A-99
A-114
ICP input format
processing algorithms
resizing
scaling
scaling factor range
size range
block diagram
block diagram
image formats
of ICP,table
bandwidth
picture
DRAM memory system
instruction cache
ICP
A-112
A-116
A-117
A-96
A-110
A-119
A-120
A-102
A-97
A-100
A-101
A-103
A-104
A-109
A-115
A-121
A-106
A-107
A-105
A-118
A-122
14-3
3-11
14-6
14-6
D
14-1
14-3
14-5
5-8
E
14-1
14-2
14-3
14-1
14-3
5-10
PRELIMINARY SPECIFICATION
F G
14-3
14-9
14-6
12-6
H
I
J
K
L M N O P Q R S T U V W X Y Z
input grid
instruction breakpoint
instruction cache
instruction cache parameters
instruction cache set
instruction cache tag
instruction cache,summary
INT_CTL
integer representation
interleaving
interrupt line
interrupt mask
interrupt mode
interrupt pin
interrupt priority
interrupt vectors
interrupts
interspersed sampling
intervals
INTVEC[31:0]
IO_ADR
IO_CTL
IO_DATA
IPENDING
IS 11172-2 references
IS 13818-2 references
ISETTING0
ISETTING1
relating to output grid
address mapping
coherency
initialization and boot
LRU replacement
performance evaluation support
PCI interface MMIO register
picture 3-12,
of SDRAM
PCI interface register
PCI interface register
definition
DSPCPU enable bit
refresh
picture
PCI interface MMIO register
picture
PCI interface MMIO register
picture
PCI interface MMIO register
picture
picture
table
picture
picture
3-9
15-3
3-9
11-10
11-10
11-10
3-11
3-10
12-6
3-9
3-10
3-10
5-11
12-6
3-10
3-9
5-8
5-9
11-10
5-8
5-8
3-13
3-4
6-5
15-3
5-8
5-11
3-2
5-10
14-7
11-9
11-9
5-8
5-8
11-15
11-13
11-13
11-13
5-12