AD9929BBCZ Analog Devices Inc, AD9929BBCZ Datasheet - Page 25

• Manufacturer Part Number: AD9929BBCZ
• Description: IC CCD SIGNAL PROCESSOR 64-BGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9929BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Table 16. Precision Timing Edge Locations for RG, H1, SHP, SHD, DCLK, and DOUTPHASE
Signal Name
RG
Signal Name
H1
Signal Name
CDS
Signal Name
Data Output [9:0]
Signal Name
DCLK1
Quadrant
I
II
III
IV
Quadrant
I
II
III
IV
Quadrant
I
II
III
IV
Quadrant
I
II
III
IV
DCLKPHASE Value
00
01
10
11
RG Rising Edge
(Not Programmable)
fixed at 000000
fixed at 000000
fixed at 000000
fixed at 000000
H1POSLOC
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
SHPLOC
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
DOUTPHASE
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
CDS Rising Edge
Data Output[9:0] Rising Edge
H1 Rising Edge
Rev. A | Page 25 of 64
Quadrant Range
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
DCLK PHASE Rising Edge
P[6]
P[16]
P[26]
P[36]
RGNEGLOC
000000 to 001011
010000 to 011011
100000 to 101011
Quadrant Range
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
Quadrant Range
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
SHDLOC
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
RG Falling Edge
CDS Falling Edge
Quadrant Range
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
H1 Falling Edge
(Not Programmable)
H1POSLOC + 24 Steps
H1POSLOC + 24 Steps
H1POSLOC + 24 Steps
H1POSLOC + 24 Steps
Data Output[9:0] Falling Edge
(Not Programmable)
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
DCLKPHASE Falling Edge
P[26]
P[36]
P[06]
P[16]
Quadrant Range
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
AD9929