AD9929BBCZ Analog Devices Inc, AD9929BBCZ Datasheet - Page 48

• Manufacturer Part Number: AD9929BBCZ
• Description: IC CCD SIGNAL PROCESSOR 64-BGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9929BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9929
VSG TIMING
The VSG Timing is controlled using the registers in Table 35.
Two unique preprogrammed VSG pulses can be configured
using the XVSGTOG_x (x = 0, 1) registers. As shown in
Figure 55, the period of the VSG pulse is set by programming
the XVSGLEN_x registers. The XVSGSELx (x = 1, 2) can then
be used to select the XVSGTOG_0 or XVSGTOG_1 pulse.
Figure 55 also shows an example of the XVSG pulse being
output in the fourth line by setting the XVSGACTLINE = 3.
The XVSG pulses references the 13-bit fixed ST counter, which
starts counting from the line set in the XVSGACTLINE register.
The 13-bit counter allows for overlapping of the XVSG pulse
into the next line if needed.
Figure 53 describes the XVSG1 and XVSG2 MUX operation
using the XVSGSELx registers.
Table 35. VSG Registers
Register
Name
XVSGMASK
XVSG_EN
XVSGTOG_0
XVSGTOG_1
XVSGLEN_0
XVSGLEN_1
XVSGSEL1
XVSGSEL2
XVSGACTLINE
OL-COUNTER
XSUBCK
9-BIT
HD
Bit
Width
6
1
11
11
8
8
1
1
7
Figure 54. Electronic Shutter Timing Example with XSUBCKMODE_HP = 1 and XSUBCKNUM_HP = 3.
Register Type
Control (Address 0x0A)
Control (Address 0x0B)
Sys_Reg(13)
Sys_Reg(13)
Sys_Reg(14)
Control (Address 0x0F)
Mode_Reg(1)
Mode_Reg(1)
Mode_Reg(1)
1
2
Reference
Counter
–
–
ST
ST
ST
ST
–
–
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Range
–
High/Low
0–8191 Pixels
0–8191 Pixels
0–255 Pixels
0–255 Pixels
High/Low
High/Low
0–128 Lines
XVSGTOG_0
XVSGTOG_1
XVSGTOG_0
XVSGTOG_1
Description
VSG Mask Control
(00 = XVSG1 Masked, XVSG2 Masked)
(02 = XVSG1 Not Masked, XVSG2 Masked)
(08 = XVSG1 Masked, XVSG2 Not Masked)
(0A= XVSG1 Not Masked, XVSG2 Not Masked)
XVSG Output Enable Control (0 = Disable
XVSG Outputs, 1 = Enable XVSG Outputs)
XVSGTOG_0 Toggle Position
XVSG TOG_1 Toggle Position
XVSGTOG_0 Pulse Width
XVSGTOG_1 Pulse Width
XVSG1 Selector
(0 = XVSGTOG_0 Applied on XVSG1,
1 = XVSGTOG_1 Applied on XVSG1)
XVSG2 Selector
(0 = XVSGTOG_0 Applied on XVSG2,
1 = XVSGTOG_1 Applied on XVSG2 )
VSG Active Line
Figure 53. XVSGSELx Registers
XVSGSEL1
XVSGSEL2
(APPLIED TO XV1)
(APPLIED TO XV3)
XVSG1
XVSG2