TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 274

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

10. Registers > Register Map
Error Diagnostic PCI/X Attributes Register
274
Bits
3:0
COMMx
EDPST (Error Diagnostic PCI/X Status): This bit is set when the PCI/X bus error
diagnostic registers are updated. This bit is cleared by writing a one to the EDPCL bit.
EDPOF (Error Diagnostic PCI/X Overflow): If the EDPST bit is clear and a PCI/X bus
error occurs, the PCI/X bus error diagnostic registers capture the PCI/X bus address and
attributes. If another error occurs and the EDPST is set, then the EDPOF bit is set and the
registers are not updated. The EDPOF bit is cleared by writing a one to the EDPCL bit.
EDPCL (Error Diagnostic PCI/X Clear): When this bit is set, all bits in the EDPAU,
EDPAL and EDPAT registers are cleared. This bit always read zero and writing a zero has no
effect.
SCD (Split Completion Discarded): This bit is set when a split completion is discarded.
This bit is only updated when the EDPST bit is clear.
USC (Unexpected Split Completion): This bit is set when an unexpected split completion is
received. This bit is only updated when the EDPST bit is clear.
SRT (Split Response Time-out): This bit is set when a split response time-out occurs. This
bit is only updated when the EDPST bit is clear.
SCEM (Split Completion Error Message): This bit is set when a split completion error
message is received. This bit is only updated when the EDPST bit is clear.
DPED (Data Parity Error Detected): This bit is set when three conditions are met: 1) the
Tsi148 asserted PERR_ itself or observed PERR_ asserted; 2) the Tsi148 was the PCI/X
Master for the transfer in which the error occurred; 3) the PERR bit in the CMMD register is
set. This bit is only updated when the EDPST bit is clear.
DPE (Detected Parity Error): This bit is set when the PCI/X Master detects a data parity
error during a read transaction or the PCI/X Target detects a parity error during a write
transaction. This bit is only updated when the EDPST bit is clear.
MRC (Maximum Retry Count): This bit is set when the maximum retry count is exceeded.
This bit is only updated when the EDPST bit is clear.
Name
Command
Function
Tsi148 PCI/X-to-VME Bus Bridge User Manual
PCFS
Space
Type
R
Reset
P/S/L
80A3020_MA001_13
By
Reset
Value
0x00