TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 85

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
PCI-X Read Transaction
The PCI-X Target uses split read transactions for all reads, which frees the PCI/X bus from
waiting for the potentially long VMEbus arbitration and transfer. Tsi148 supports up to six
split reads.
When the PCI-X Target receives a read request, the PCI-X Target saves the information
required to complete the transfer and then issues a Split Response termination to the PCI-X
bus master. This allows the PCI-X bus to be used by other PCI-X bus masters while Tsi148
completes the transfer. If the PCI-X Target receives a read request from a PCI-X bus master
and the PCI-X Target read buffer command queue is full, the PCI-X Target retries the PCI-X
bus master until there is space available in the read buffer.
After the PCI-X Target has issued the Split Response to the PCI-X bus master, the PCI-X
Target then issues a read command to the Linkage Module for the requested byte count. As
defined in the PCI-X Addendum to PCI Local Bus Specification (Revision 1.0b), byte counts
up to 4 Kbyte are supported.
When the data is returned from the VME Master through the Linkage Module to the PCI-X
Target read buffer, the Tsi148 PCI-X Master initiates a Split Completion and transfers the data
from the PCI-X Target read buffer to the requesting PCI-X bus master. If the requested read
extends past the ending address defined by the Target Image (see
page
transaction with a Split Completion Error Message to the initiating PCI-X bus master (see
Section 3.3.3.1 on page
233), the PCI-X Master provides data up to the end of the image and then terminates the
For more information on the PCI-X implementation of split reads, refer to the
PCI-X Addendum to PCI Local Bus Specification (Revision 1.0b).
A Split Response means PCI-X Target does not have to issue retries as the read is
being completed on the VMEbus while waiting for the requested data.
93).
3. PCI/X Interface > PCI-X Mode
Section 10.4.20 on
85