TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 31

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

1.2.3
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
Refer to the Source Synchronous Transfer (2eSST) Standard for more information on the
2eSST protocol.
VME Slave
The Tsi148 VME Slave accepts most of the addressing and data transfer modes documented
in the VME64 Specification, the VME64x Specification, and Source Synchronous Transfer
(2eSST) Standard specification. The supported transactions include:
•
•
•
•
•
•
Incoming write transactions from the VMEbus are posted. With posted write transactions,
data is written to a VME Slave write buffer. The VME Slave write buffer is a 4 Kbyte buffer.
When the Tsi148 VME Slave accepts a write request, the initiating VMEbus master receives a
data acknowledgment from Tsi148. Write data is transferred from the VME Slave write
buffer, through the internal Linkage Module, to the PCI/X Master write buffer without
involving the initiating VMEbus master. Refer to
description of transaction flow and buffer usage in Tsi148.
The VME Slave read operations depend on whether the transfer is a SCT or BLT transfer. If
the transfer is a SCT transfer, the VME Slave requests a single beat transfer from the Linkage
Module (see
master initiates a block read (BLT, MBLT, 2eVME, or 2eSST) transaction on the VMEbus.
When the Tsi148 PCI/X Master receives a read request (after the VME Slave sends the read
request requirements through the Linkage Module) , the PCI/X Master fills its read buffer by
issuing burst requests to the PCI/X bus target.
The VME Slave read buffer is a 2 Kbyte read buffer with a programmable size and refill
threshold . The design enables the initiating VMEbus master to acquire its block read data
from the VME Slave (after the PCI/X Master has transferred the data through the Linkage
Module to the VME Slave ) instead of directly from the PCI/X resources.
Address: A16, A24, A32, and A64
Data: D8, D16, and D32 Single Cycle Transaction (SCT)
Data: D8, D16, D32 Block Transaction (BLT)
Data: D64 Multiple Block Transaction (MBLT)
Data: D64 2eVME
Data: D64 2eSST
Section 1.4 on page
37). A PCI/X prefetched read is initiated when a VMEbus
Section 2.2.1 on page 44
1. Functional Overview > VMEbus Interface
for a detailed
31