TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 358

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

10. Registers > Register Map
Control and Status Register
358
12:8
Bits
7:0
LRST (Local Reset): When this bit is set. the LRSTO_ signal is asserted. When this bit is
cleared, the LRSTO_ signal is not asserted. When this bit is set and cleared, the Tsi148
ensures the minimum pulse width for local reset is met.
SFAILEN (System Fail Enable): When this bit is set and the BDFAIL_ signal is asserted, the
SFAILO signal line is asserted. When this bit is cleared, the SFAILO signal line is not
asserted. The initial value of this bit is a configuration option.
The system fail enable bit is also accessible in the CR/CSR.
BDFAILS (Board Fail Status): Reading a one indicates the BDFAIL_ signal is asserted.
Reading a zero indicates the BDFAIL_ signal is not asserted.
SCONS (System Controller Status): Reading a one indicates, the VMEbus system controller
is enabled.
MEN (Module Enable): This is a read/write bit that can be used to indicate a ready
condition. The READY is cleared by reset. Software may set this bit, after the board is
initialized, to indicate the board is ready.
LMI3S (Location Monitor Interrupt 3 Status): When set, a location monitor 3 interrupt is
pending.
LMI2S (Location Monitor Interrupt 2 Status): When set, a location monitor 2 interrupt is
pending.
LMI1S (Location Monitor Interrupt 1 Status): When set, a location monitor 1 interrupt is
pending.
LMI0S (Location Monitor Interrupt 0 Status): When set, a location monitor 0 interrupt is
pending.
MBI3S (Mail Box Interrupt 3 Status): When set, a mail box 3 interrupt is pending.
MBI2S (Mail Box Interrupt 2 Status): When set, a mail box 2 interrupt is pending.
MBI1S (Mail Box Interrupt 1 Status): When set, a mail box 1 interrupt is pending.
REVID
Name
GA
Geographic Address
Revision ID
Function
Tsi148 PCI/X-to-VME Bus Bridge User Manual
PCFS
Space
Type
R
R
Reset
80A3020_MA001_13
By
-
-
Reset
Value
0x01
0xxx