TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 69

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

3.2.1.2
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
Transaction Mapping
The PCI bus is capable of many different transaction types, including: single beat
transactions, burst transactions, each with flexible byte enable patterns. These transactions
must be mapped to corresponding transactions on the VMEbus. There are many different
modes and protocols supported by the VMEbus and the numerous programmable options.
The following rules can be applied to transactions:
•
•
PCI-to-VME Address Mapping
The PCI Target has eight programmable PCI bus target images which map PCI transactions to
VME address space.
The PCI Target maps a PCI address to the destination address space using eight
programmable target images. These target images provide windows into the VMEbus from
the PCI bus. The PCI address is compared with the address range of each target image, and if
the address falls within the specified range, an offset is added to the incoming address to form
the destination address.
Writes
— During a PCI bus write, the selected bytes on the PCI bus maps directly to the
Reads
— Single byte reads on PCI maps to a single byte read on the destination bus. If the PCI
— Read line and read multiple commands from a PCI Master causes data to be
— The PCI Target does not merge, combine, or gather transactions. Because of the
destination bus. The chip does not write to bytes on the destination bus that are not
selected on the PCI bus.
Master inserts initial wait states during a read transaction (IRDY_ is not asserted one
clock after FRAME_), the transaction is a burst and the PCI Target prefetches data
from the VMEbus based on the programming in the Outbound Translation Attribute
register (see
prefetched from the VMEbus based on the programming in the Outbound
Translation Attribute Register.
different bus widths, a single beat transaction on the PCI bus may map to a multi beat
transaction on the destination bus. A transaction that completes in a single bus tenure
on the PCI bus may not complete in a single bus tenure on the destination bus.
Any locations with read sensitive bits should be accessed using a byte read or a
read that matches the width of the location. There is a one-to-one correspondence
between the bytes written on the PCI bus and bytes written on the destination bus.
PCI bus writes with byte holes do not result in writes to the non-selected bytes.
Section 10.4.26 on page
239).
3. PCI/X Interface > PCI Mode
69