TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 45

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

2.2.1.1
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
The single write buffer receives data and commands from the VMEbus. The write buffer is
segmented into two parts: data queue and command queue. The data queue designed for large
burst transfers and supports up to 4 Kbyte of data. The command queue stores address and
command information and can accept six entries. The write buffer is considered full when
either the command or data queue is full.
Transaction Mapping
The VMEbus is capable of many different transaction types, including one to four byte single
beat transactions and burst transactions. These transactions must be mapped to corresponding
transactions on the PCI/X bus. The Tsi148 supports all the different modes and protocols
supported by the PCI/X bus and has numerous programmable options. Because of this
flexibility there are many possible types of transactions between VME and PCI/X. The
following rules can be applied to transactions:
1. A one, two, three, or four byte read or write on the VMEbus always maps to a
2. The VME Slave does not merge, combine, or gather transactions. A transaction that
3. The VME Master does not generate the two and three byte unaligned transactions defined
VMEbus-to-PCI Address Mapping
The VME Slave interface maps a VMEbus address to the PCI/X bus address space using eight
programmable slave images (see
windows into the PCI/X bus from the VMEbus. The VMEbus address is compared with the
address range of each slave image, and if the address falls within the specified range, an offset
is added to the incoming address to form the PCI/X bus address.
The incoming address is within the slave images window if the incoming address is greater
than or equal to the starting address and less than or equal to the ending address.
corresponding read or write on the destination bus. VMEbus block reads can cause data
to be prefetched from the PCI/X bus. Any locations with read sensitive bits should be
accessed using a Single cycle Transaction (SCT) read that matches the width of the
location. There is a one-to-one correspondence between the bytes written on the VMEbus
and bytes written on the PCI/X bus.
completes in a single bus tenure on the VMEbus may not complete in a single bus tenure
on the destination bus.
in the American National Standard for VME64.
All programmable slave images should decode unique address ranges. However,
if the slave images overlap, slave image zero has the highest priority and slave
image seven has the lowest priority.
Section 10.4.46 on page
277). These slave images provide
2. VME Interface > VME Slave
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