TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 68

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

3. PCI/X Interface > Overview of the PCI/X Interface
3.1
3.2
3.2.1
3.2.1.1
68
Overview of the PCI/X Interface
The PCI/X interface can be configured to operate in PCI mode or PCI-X mode. PCI-X mode
is described in
PCI Mode
Tsi148 is compliant with the PCI Local Bus Specification (Revision 2.2).
PCI Target
The PCI Target supports the PCI protocol, 32-bit and 64-bit data transfers, and 32-bit and
64-bit addresses.
The PCI Target supports configuration cycles to PCI configuration registers and memory
space accesses. The Linkage Module provides access to the Combined Register Group (CRG)
and the VMEbus (see
Master provides the interface between the Linkage Module and the VMEbus.
The PCI Target does not respond to PCI I/O transfers.
PCI Target Buffers
The PCI Target shares buffers between the PCI and PCI-X protocols. When the PCI/X bus is
configured for PCI mode, only 512 bytes of the 4 Kbyte read buffer can be used. The read
buffer is segmented into two parts: a data queue and a command queue. The command queue
stores address and command information from the PCI bus and can accept one delayed
transaction. The data queue stores up to 512 bytes of data.
The PCI Target stores the address and command information in the command queue when
servicing a read request from the PCI bus master. The amount of data pre-fetched and stored
in the read buffer is determined by the read command (see
The write buffer receives data and commands from the PCI bus. The write buffer is
segmented into two parts: data queue and command queue. The 4 Kbyte data queue is
designed for large, burst transfers. The command queue stores address and command
information and can accept up to 40 entries. The write buffer is full when either the command
or data queue is full.
Section 3.3 on page
Section 10.1 on page 192
82.
for more register information). The VME
Tsi148 PCI/X-to-VME Bus Bridge User Manual
Table 3 on page
80A3020_MA001_13
72).