TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 63

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

2.3.6.3
2.3.6.4
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
Mailbox Registers
The GCSR includes four mailbox registers which can be used to provide a communication
path between the VMEbus and the PCI/X bus. These registers support read and write access
from the PCI/X bus and the VMEbus. When the least significant byte of a mailbox register is
written, an interrupt is sent to the interrupter. If the interrupt is enabled, an INTx signal is
generated.
Broadcast Interrupt and 64-bit Counter
There are two Tsi148 VMEbus features which use the IRQ[1]_ or IRQ[2]_ signal lines in a
device specific way: the Broadcast Interrupt and 64-bit Counter.
The IRQ[1]_ and IRQ[2]_ signal lines received from the VMEbus can be routed to several
internal modules. They are always sent to the local bus interrupter as standard interrupts. They
may be sent to the local bus interrupter as an edge sensitive interrupt or they can be sent to a
64-bit counter.
The following functions can be assigned to the IRQ[1] or IRQ[2] signal lines:
•
•
•
•
VMEbus Interrupter: The VMEbus interrupter allows VMEbus interrupts to be generated
as defined in the VMEbus standard. For more information see
page
Programmable Pulse Generator: This generator allows a pulse on the VMEbus IRQ[1]O
or IRQ[2]O signal line to be generated. The width of the pulse generated is
programmable from 120 ns to 1.97 ms in approximately 30ns increments.
Programmable Clock Generator: Enables a free running clock to be generated on IRQ[1]
or IRQ[2]. The period of the clock generator is programmable from 2.04us to 17.11sec in
approximately 1.02us increments. This provides frequencies from 0.49MHz to 0.06Hz.
Fixed 0.98MHz clock: Generated on IRQ[1] or IRQ[2] signal line.
133.
RMW access to a mailbox register from the VMEbus is not guaranteed to be
indivisible. The semaphore registers should be used to control access if the RMW
feature is required.
When the IRQ[1]_ or IRQ[2]_ signal lines are used for the Broadcast Interrupt or
64-bit Counter features, they must not be used for VMEbus interrupt signals by
any other boards. These features are not defined in the VMEbus standards. The
features can be programmed in the VMEbus Interrupt Control registers (see
Section 10.4.70 on page
309).
2. VME Interface > VME Master
“Interrupt Controller” on
63