PEB20256EV21GXP Infineon Technologies, PEB20256EV21GXP Datasheet - Page 159

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PEB20256EV21GXP

Manufacturer Part Number
PEB20256EV21GXP
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB20256EV21GXP

Operating Supply Voltage (typ)
2.5/3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
CSPEC_IMASK
Channel Specification Interrupt Vector Mask Register
Access
Address
Reset Value
For each channel or command related interrupt vector an interrupt vector generation
mask is provided. Generation of an interrupt vector itself does not necessarily result in
assertion of the interrupt pin. For description of interrupt concept and interrupt vectors
see
The following definition applies:
1
0
Channel Interrupt Vector Transmit
TAB
HTAB
UR
TFE
Command Interrupt Vector Transmit
TTC
Data Sheet
31
15
0
0
Chapter 4.7.1
RAB
TAB
30
14
RFE HRAB MFL RFOD CRC ILEN RFOP
13
0
: read/write
: 02C
: 00000000
The device will not generate the corresponding interrupt vector, i.e. the
interrupt vector is masked.
An interrupt condition results in generation of the corresponding interrupt
vector.
Mask ’Transmit Abort’
Mask ’Hold Caused Transmit Abort’
Mask ’Transmit Underrun’
Mask ’Transmit Frame End’
Mask ’Transmit Command Complete’
HTAB
.
28
12
H
11
0
H
10
0
0
9
0
8
159
UR
23
7
TFE
SF
22
6
IFTC
0
5
0
0
Register Description
SFD
0
3
SD
PEB 20256 E
PEF 20256 E
0
2
0
0
04.2001
TCC
RCC
16
0

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