PEB20256EV21GXP Infineon Technologies, PEB20256EV21GXP Datasheet - Page 80

• Manufacturer Part Number: PEB20256EV21GXP
• Manufacturer: Infineon Technologies

Specifications of PEB20256EV21GXP

• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

This interrupt vector will be written to the interrupt queue specified in CONF1.SYSQ and
together with this the pin INTA will be asserted. The processor sees the interrupt pin
asserted, reads the register GISTA in order to determine the interrupt queue, and then
writes a ‘1’ to the interrupt status acknowledge register GIACK to clear the interrupt.
Next, it reads the interrupt vector which contains a copy of the mailbox status register
and then reads the mailbox data registers.
4.7
All layer two interrupts (channel, port, system and command interrupts) are handled via
an internal interrupt controller which forwards those interrupts to external interrupt
queues. This interrupt controller is connected to the PCI interrupt pin INTA.
Mailbox interrupts are handled via an internal interrupt FIFO which is connected to the
local bus interrupt pin LINT (normal operation). Additionally the interrupts stored in the
internal interrupt FIFO can be notified via the PCI interrupt pin INTA.
The MUNICH256 also provides the capability to bridge the local bus interrupt LINT to the
PCI bus.
4.7.1
All channel interrupts, port interrupts and system interrupts are written in form of interrupt
vectors to interrupt queues.
Each interrupt vector has an interrupt source. An interrupt source is either a channel, the
port handler or certain device functions (system interrupts). After reset no interrupt vector
is generated since port and system interrupts are masked and channels are in their idle
state.
Each interrupt source forwards its interrupt vector to the interrupt controller, together with
the information in which interrupt queue the vector should be forwarded. The interrupt
controller moves the interrupt vector to the selected interrupt queue. Channel interrupts
can optionally be forwarded to a dedicated high priority interrupt queue (interrupt queue
seven). A programmable interrupt queue high priority mask determines channel
interrupts, which shall be forwarded into the high priority interrupt queue instead of
queueing them in the selected interrupt queue. This function is available for each
interrupt queue and allows to queue important interrupt conditions in the high priority
queue.
Data Sheet
Interrupt Controller
Layer Two interrupts
80
Functional Description
PEB 20256 E
PEF 20256 E
04.2001