PEB20256EV21GXP Infineon Technologies, PEB20256EV21GXP Datasheet - Page 48

• Manufacturer Part Number: PEB20256EV21GXP
• Manufacturer: Infineon Technologies

Specifications of PEB20256EV21GXP

• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

PEB 20256 E
PEF 20256 E
General Overview
• The interrupt busses, which collect all interrupt information and forward them to the
corresponding interrupt handler.
The chip’s core functions are all operated with the PCI clock. Transfers between clocking
regions (serial clocks and system clock) are implemented only in the serial interface.
3.4
Block Description
The following section gives a brief overview to the function of each block. For a detailed
description of each function refer to
“Functional Description” on Page 5 1
.
Serial port interface
The Serial Port Interface consists of the subfunctions receive and transmit. This block
provides the function of serial/parallel and parallel/serial conversion for up to 16 (or 28
when configured for 28 port mode) incoming and outgoing serial data streams. Serial
data is then transferred between the internal clocking system, which is derived from the
PCI clock, and the various line clocks. This provides a unique clocking scheme on the
internal interfaces. The aggregate bandwidth of all enabled ports can be up to 90 MBit/
s in each direction with a PCI clock frequency of 66 MHz.
Time slot assigner
The time slot assigner exchanges data with the serial interface on a 8 bit parallel bus,
thus funneling all data of up to 28 interfaces. The time slot assigner provides freely
programmable mapping of any time slot or any combination of time slots to 256 logical
channels. A programmable mask can be provided to allow subchanneling of the
available time slots which allows channel data rates starting at 8kbit/s.
At the protocol machine interface the time slot assigner and the protocol machine
exchanges channel oriented data (8 bit) together with the time slots masks.
Protocol handler
Two protocol machines, one for receive direction and one for transmit direction, provide
protocol handling for up to 256 logical channels and a maximum serial aggregate data
rate of up to 90 Mbit/s per direction. The protocol machines implement four modes, which
can be programmed independently for each logical channel: HDLC, bit-synchronous
PPP, octet-synchronous PPP and Transparent Mode A, including frame synchronous
TMA.
Internal buffer
The internal buffers provides channelwise buffering of raw (unformatted/deformatted)
data for 256 logical channels. Channel specific thresholds can be programmed
Data Sheet
48
04.2001