PEB20256EV21GXP Infineon Technologies, PEB20256EV21GXP Datasheet - Page 85

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PEB20256EV21GXP

Manufacturer Part Number
PEB20256EV21GXP
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB20256EV21GXP

Operating Supply Voltage (typ)
2.5/3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
4.7.1.3
Port interrupt vectors indicate the synchronous or asynchronous state of a port.
Immediately after enabling both, the port and the port interrupts, port interrupts are
generated indicating the synchronous or asynchronous state of a port. After this initial
interrupt vector generation, further interrupts are written only when the state of a port
changes from synchronous state to asynchronous state or vice versa. Port interrupts are
enabled by resetting the corresponding mask bit in register PMR.
Transmit interrupts
PORT
SYN
ASYN
Data Sheet
31
15
1
0
30
0
10
Port Interrupts
B
29
0
Port Number
This bit field identifies the port for which the information in the interrupt
vector is valid.
Synchronization achieved
Port has changed from asynchronous state to synchronous state. This
interrupt is available for ports configured in T1 or E1, 4.096 MHz mode
or 8.192 M H z mode. In unchannelized mode there is no synchronous
state.
A transmit port changes to the synchronous state if the number of bits
between two synchronization pulses is equal to a multiple of the number
of frame bits of the selected mode. The first synchronization pulse after
a port is enabled causes the port to change to the synchronous state.
Asynchronous State
The transmitter generates an ’Asynchronous State’ interrupt vector if a
port has changed from synchronous to asynchronous state. This
interrupt is available for ports configured in T1, E1, 4.096MHz mode or
8.192 MHz mode. In unchannelized mode there is no asynchronous
state. In general a port is in asynchronous state when a port is disabled.
A port changes to the asynchronous state if the number of bits between
two synchronization pulses is not equal to a multiple of the number of
frame bits of the selected mode.
28
0
10
B
27
0
26
0
QUEUE(2:0)
0
24
0
85
0
0
0
0
0
5
0
0
4
Functional Description
0
PORT(4:0)
PEB 20256 E
PEF 20256 E
0
SYN ASYN
17
04.2001
16
0

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