MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 106

MC68HC908LD60IFU

Manufacturer Part Number
MC68HC908LD60IFU
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC908LD60IFU

Cpu Family
HC08
Device Core Size
8b
Frequency (max)
6MHz
Program Memory Type
Flash
Program Memory Size
60KB
Total Internal Ram Size
1KB
# I/os (max)
39
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
6-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Package Type
PQFP
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908LD60IFU
Manufacturer:
FREESCALE
Quantity:
840
Clock Generator Module (CGM)
8.8.2 Stop Mode
8.9 CGM During Break Interrupts
Technical Data
106
When the STOP instruction executes, the SIM drives the SIMOSCEN
signal low, disabling the CGM and holding low all CGM outputs
(OSCXCLK, DCLK1, and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
driving DCLK1, the PLL automatically clears the BCS bit in the PLL
control register (PCTL), thereby selecting the crystal clock, OSCXCLK,
as the source of DCLK1. When the MCU recovers from STOP, the
crystal clock drives DCLK1 and BCS remains clear.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See
Module
To allow software to clear status bits during a break interrupt, a 1 should
be written to the BCFE bit. If a status bit is cleared during the break state,
it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a 0 to the BCFE bit.
With BCFE at 0 (its default state), software can read and write the PLL
control register during the break state without affecting the PLLF bit.
(SIM).
Clock Generator Module (CGM)
Section 9. System Integration
MC68HC908LD60
Freescale Semiconductor
Rev. 1.1

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