MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 147

MC68HC908LD60IFU

Manufacturer Part Number
MC68HC908LD60IFU
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC908LD60IFU

Cpu Family
HC08
Device Core Size
8b
Frequency (max)
6MHz
Program Memory Type
Flash
Program Memory Size
60KB
Total Internal Ram Size
1KB
# I/os (max)
39
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
6-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Package Type
PQFP
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908LD60IFU
Manufacturer:
FREESCALE
Quantity:
840
11.5.1 TIM Counter Prescaler
11.5.2 Input Capture
11.5.3 Output Compare
MC68HC908LD60
Freescale Semiconductor
$0014
$0015
Addr.
Register Name
TIM Channel 1
TIM Channel 1
Register High
Register Low
Rev. 1.1
(TCH1H)
(TCH1L)
The TIM clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIM status and control register
(TSC) select the TIM clock source.
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.
Reset:
Reset:
Read:
Read:
Write:
Write:
Bit15
Bit 7
Bit7
Timer Interface Module (TIM)
= Unimplemented
Bit14
Bit6
6
Bit13
Bit5
5
Indeterminate after reset
Indeterminate after reset
Bit12
Bit4
4
Bit11
Bit3
3
Timer Interface Module (TIM)
Bit10
Bit2
2
Functional Description
Bit9
Bit1
1
Technical Data
Bit 0
Bit8
Bit0
147

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