MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 186

MC68HC908LD60IFU

Manufacturer Part Number
MC68HC908LD60IFU
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC908LD60IFU

Cpu Family
HC08
Device Core Size
8b
Frequency (max)
6MHz
Program Memory Type
Flash
Program Memory Size
60KB
Total Internal Ram Size
1KB
# I/os (max)
39
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
6-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Package Type
PQFP
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908LD60IFU
Manufacturer:
FREESCALE
Quantity:
840
Multi-Master IIC Interface (MMIIC)
14.5.3 Multi-Master IIC Master Control Register (MIMCR)
Technical Data
186
Address:
MMALIF — Multi-Master Arbitration Lost Interrupt Flag
MMNAKIF — No Acknowledge Interrupt Flag
MMBB — Bus Busy Flag
Reset:
Figure 14-4. Multi-Master IIC Master Control Register (MIMCR)
Read: MMALIF MMNAKIF
Write:
This flag is set when software attempt to set MMAST but the MMBB
has been set by detecting the start condition on the lines or when the
MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA
line in master mode – an arbitration loss. This bit generates an
interrupt request to the CPU if the MMIEN bit in MMCR is also set.
This bit is cleared by writing "0" to it or by reset.
This flag is only set in master mode (MMAST = 1) when there is no
acknowledge bit detected after one data byte or calling address is
transferred. This flag also clears MMAST. MMNAKIF generates an
interrupt request to CPU if the MMIEN bit in MMCR is also set. This
bit is cleared by writing "0" to it or by reset.
This flag is set after a start condition is detected (bus busy), and is
cleared when a stop condition (bus idle) is detected or the MMIIC is
disabled. Reset clears this bit.
1 = Lost arbitration in master mode
0 = No arbitration lost
1 = No acknowledge bit detected
0 = Acknowledge bit detected
1 = Start condition detected
0 = Stop condition detected or MMIIC is disabled
$006A
Bit 7
Multi-Master IIC Interface (MMIIC)
0
0
6
0
0
MMBB
5
0
MMAST
4
0
MMRW
3
0
MC68HC908LD60
MMBR2
Freescale Semiconductor
2
0
MMBR1
1
0
MMBR0
Rev. 1.1
Bit 0
0

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