MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 196

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

DDC12AB Interface
15.3 Features
15.4 I/O Pins
Technical Data
196
Generic Pin Names:
DDC12AB
SDA
SCL
This DDC12AB module uses the DDCSCL clock line and the DDCSDA
data line to communicate with external DDC host or IIC interface. These
two pins are shared with port pins PTD4 and PTD5 respectively. The
outputs of DDCSDA and DDCSCL pins are open-drain type — no
clamping diode is connected between the pin and internal V
maximum data rate typically is 100k-bps. The maximum communication
length and the number of devices that can be connected are limited by
a maximum bus capacitance of 400pF.
The DDC12AB module uses two I/O pins, shared with standard port I/O
pins. The full name of the DDC12AB I/O pins are listed in
The generic pin name appear in the text that follows.
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Table 15-1. Pin Name Conventions
DDC1 hardware
Compatibility with multi-master IIC bus standard
Software controllable acknowledge bit generation
Interrupt driven byte by byte data transfer
Calling address identification interrupt
Auto detection of R/W bit and switching of transmit or receive
mode
Detection of START, repeated START, and STOP signals
Auto generation of START and STOP condition in master mode
Arbitration loss detection and No-ACK awareness in master mode
8 selectable baud rate master clocks
Automatic recognition of the received acknowledge bit
Full MCU Pin Names:
PTD5/DDCSDA
PTD4/DDCSCL
DDC12AB Interface
DDCSCLE bit in PDCR ($0069)
DDCDATE bit in PDCR ($0069)
DDC Function By:
Pin Selected for
MC68HC908LD60
Freescale Semiconductor
Table
DD
. The
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15-1.
Rev. 1.1