MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 23

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

MC68HC908LD60
Freescale Semiconductor
—
Rev. 1.1
Figure
11-6 TIM Channel Status and Control Registers (TSC0:TSC1) . . . 159
11-7 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
11-8 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . . 163
12-1 PWM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 166
12-2 PWM Data Registers 0 to 7 (0PWM–7PWM) . . . . . . . . . . . . . 167
12-3 PWM Control Register (PWMCR). . . . . . . . . . . . . . . . . . . . . . 168
12-4 8-Bit PWM Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 169
13-1 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 172
13-2 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
13-3 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 177
13-4 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
13-5 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . . 179
14-1 MMIIC I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . 183
14-2 Multi-Master IIC Address Register (MMADR). . . . . . . . . . . . . 184
14-3 Multi-Master IIC Control Register (MMCR). . . . . . . . . . . . . . . 185
14-4 Multi-Master IIC Master Control Register (MIMCR) . . . . . . . . 186
14-5 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . . . 188
14-6 Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . . . 190
14-7 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . . . 191
14-8 Data Transfer Sequences for Master/Slave
15-1 DDC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 197
15-2 DDC Address Register (DADR) . . . . . . . . . . . . . . . . . . . . . . .198
15-3 DDC2 Address Register (D2ADR) . . . . . . . . . . . . . . . . . . . . . 199
15-4 DDC Control Register (DCR) . . . . . . . . . . . . . . . . . . . . . . . . . 200
15-5 DDC Master Control Register (DMCR). . . . . . . . . . . . . . . . . . 201
15-6 DDC Status Register (DSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 204
15-7 DDC Data Transmit Register (DDTR). . . . . . . . . . . . . . . . . . . 206
15-8 DDC Data Receive Register (DDRR) . . . . . . . . . . . . . . . . . . . 207
15-9 Data Transfer Sequences for Master/Slave
Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 209
List of Figures
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Technical Data
List of Figures
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