DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 168
DS2156L+
Manufacturer Part Number
DS2156L+
Description
IC TXRX T1/E1/J1 1-CHIP 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2156L.pdf
(265 pages)
Specifications of DS2156L+
Function
Single-Chip Transceiver
Interface
E1, J1, T1, TDM, UTOPIA II
Number Of Circuits
1
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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24.
24.1 Description
The DS2156’s UTOPIA interface maps the ATM cells in a T1/E1 frame in the transmit direction as per
ATM Forum Specifications af-phy-0016.000 [1] and af-phy-0064.000 [2] and recovers them in the
receive direction from a similar mapping. In the receive direction, the cell delineation mechanism used
for finding ATM cell boundaries within a T1/E1 frame is performed as per ITU-T I.432 [4]. The terms
“physical layer (PHY)” and “line side” are used synonymously in this document and refer to the device
interface with the line side of the DS2156. The terms “ATM layer” and “system side” are used
synonymously and refer to the UTOPIA-II interface of the DS2156.
The transmit section receives cells from the ATM layer through the UTOPIA-II interface. It writes the
cells into a 4-cell-deep transmit FIFO that is used for rate decoupling. The FIFO’s depth is programmable
to two, three, or four ATM cells. The cells are mapped into the T1/E1 frame as per [1] and [2]. The
DS2156 can be configured to perform valid HEC insertion and payload scrambling.
The receive section delineates the cells from the data received from the PHY layer as per [4]. Once cells
are delineated, they are written into a 4-cell-deep receive FIFO used for rate decoupling. The receive
section interfaces with the ATM layer through the UTOPIA-II interface. It can also be configured to
perform payload descrambling and idle/unassigned cell filtering. Single-bit HEC error correction is also
supported.
24.1.1
1) ATM Forum “DS1 Physical Layer Specification,” af-phy-0016.000, September 1994
2) ATM Forum “E1 Physical Layer Specification,” af-phy-0064.000, September 1996
3) ATM Forum “UTOPIA Level 2 Specification,” Version 1.0, af-phy-0039.000, June 1995
4) B-ISDN User-Network Interface—Physical Layer Specification—ITU-T Recommendation I.432–
24.1.2
ATM
CRC
HEC
LCD
OAM
OCD
PMON
UTOPIA
ACRONYM
03/93
UTOPIA BACKPLANE INTERFACE
List of Applicable Standards
Acronyms and Definitions
Asynchronous Transfer Mode
Cyclic Redundancy Check
Header Error Check
Loss-of-Cell Delineation
Operations Administration and Maintenance
Out-of-Loss Delineation
Performance Monitoring
Universal Test and Operations PHY Interface for ATM
DEFINITION
168 of 265
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