DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 56

• Manufacturer Part Number: DS2156L+
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2156L+

• Function: Single-Chip Transceiver
• Interface: E1, J1, T1, TDM, UTOPIA II
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS)
Bit 1/Transmit-Side ZBTSI Support Enable (TZBTSI). Allows ZBTSI information to be input on TLINK pin.
Bit 2/Transmit-Side D4 Yellow Alarm Select (TD4YM)
Bit 3/F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft
(D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of
synchronization.
Bit 4/F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode)
or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.
Bit 5/Transmit FDL Zero-Stuffer Enable (TZSE). Set this bit to 0 if using the internal HDLC controller instead
of the legacy support for the FDL. See Section 15 for details.
Bit 6/Transmit SLC-96/Fs-Bit Insertion Enable (TSLC96). Only set this bit to a 1 in D4 framing applications.
Must be set to 1 to source the Fs pattern from the TFDL register. See Section 22.6 for details.
Bit 7/Transmit B8ZS Enable (TB8ZS)
0 = no stuffing occurs
1 = bit 7 forced to a 1 in channels with all 0s
0 = ZBTSI disabled
1 = ZBTSI enabled
0 = 0s in bit 2 of all channels
1 = a 1 in the S-bit position of frame 12
0 = zero stuffer disabled
1 = zero stuffer enabled
0 = SLC-96/Fs-bit insertion disabled
1 = SLC-96/Fs-bit insertion enabled
0 = B8ZS disabled
1 = B8ZS enabled
TB8ZS
7
0
TSLC96
T1TCR2
T1 Transmit Control Register 2
06h
6
0
TZSE
5
0
FBCT2
4
0
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FBCT1
3
0
TD4YM
2
0
TZBTSI
1
0
TB7ZS
0
0