DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 180

• Manufacturer Part Number: DS2156L+
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2156L+

• Function: Single-Chip Transceiver
• Interface: E1, J1, T1, TDM, UTOPIA II
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

DS2156
Figure 24-10 shows a case when, after the end of transmission of a cell from PHY N, no other PHY has a
cell available. Therefore, UR-ENB remains asserted as the ATM assumes a cell-available from PHY N.
With clock edge #9, it turns out that PHY N also has no cell available, as UR-SOC remains low. The
ATM then deasserts UR-ENB while the polling of the PHYs continues. With clock edge #15,
PHY N - 3 is found to have a cell for transmission. Thus, address N - 3 is applied and the PHY N - 3 is
selected with clock edge #16. Additional receive interface examples are available in [3].
Figure 24-10. End and Restart of Cell Transmission at Receive Interface
SELECTION
DETECTION
POLLING
POLLING
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
UR-CLK
UR-ADDRx
N-3
1F
N+1
1F
N-1
1F
N
1F
N+3
1F
N-1
1F
N-3
1F
N-3
1F
N+1
1F
N+2
N-3
N-3
UR-CLAV
N-3
N+1
N-1
N
N+3
N-1
N+1
UR-ENB
UR-DATAx
P42 P43 P44
P45 P46 P47 P48
XX
H1
H2
H3
UR-SOC
CELL RCV FROM:
PHY N
PHY N-3
24.6.3
UTOPIA Side Receive: Direct Status Mode (Multireceive CLAV)
Up to a maximum of four PHY ports can be connected to one ATM layer. For each PHY port, the status
signals UR-CLAV and UT-CLAV are permanently available according to UTOPIA Level 1 specification.
Status signals and cell transfers are independent of each other. No address information is needed to obtain
status information. Address information must be valid only for selecting a PHY port prior to one or
multiple cell transfers. With respect to the status signals UR-CLAV and UT-CLAV, this mode of
operation corresponds to that of four individual PHY devices according to UTOPIA Level 1. With respect
to the cell transfer, this mode of operation corresponds to that as described in this document and [3]. The
ATM layer selects a PHY port for cell transfer by placing the desired port on the address lines
(UR-ADDRx, UT-ADDRx), while the enable signal (UR-ENB, UT-ENB) is deasserted. All PHY ports
only examine the value on the address lines for possible selection when the enable signal is deasserted. In
case the ATM suspends transmission for a specific PHY port during a cell transfer, no cells to/from other
PHY ports can be transferred during this time.
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