DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 222

• Manufacturer Part Number: DS2156L+
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2156L+

• Function: Single-Chip Transceiver
• Interface: E1, J1, T1, TDM, UTOPIA II
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

30.
The DS2156 contains an on-chip clock synthesizer that generates a user-selectable clock output on the
BPCLK pin, referenced to the recovered receive clock (RCLK). The synthesizer uses a phase-locked loop
to generate low-jitter clocks. Common applications include generation of port and backplane system
clocks. The CCR2 register is used to enable (CCR2.0) and select (CCR2.1 and CCR2.2) the clock
frequency of the BPCLK pin.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Backplane Clock Enable (BPEN)
Bits 1, 2/Backplane Clock Selects (BPCS0, BPCS1)
Bits 3 to 7/UTOPIA Port Address (TRPA0 to TRPA4). See Register Definitions in Section 24.7.
31.
31.1 TDM Backplane Mode
The DS2156 can be programmed to output gapped clocks for selected channels in the receive and
transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-
PRI applications. The receive and transmit paths have independent enables. Channel formats supported
include 56kbps and 64kbps. This is accomplished by assigning an alternate function to the RCHCLK and
TCHCLK pins. Setting CCR3.0 = 1 causes the RCHCLK pin to output a gapped clock as defined by the
receive fractional T1/E1 function of the PCPR register. Setting CCR3.2 = 1 causes the TCHCLK pin to
output a gapped clock as defined by the transmit fractional T1/E1 function of the PCPR register. CCR3.1
and CCR3.3 can be used to select between 64kbps and 56kbps operation. See Section 5 for details about
programming the per-channel function. In T1 mode no clock is generated at the F-bit position.
When 56kbps mode is selected, the LSB clock in the channel is omitted. Only the seven most significant
bits of the channel have clocks.
BPCS1
0
0
1
1
PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER
0 = disable BPCLK pin (pin held at logic 0)
1 = enable BPCLK pin
FRACTIONAL T1/E1 SUPPORT
TRPA4
7
0
BPCS0
0
1
0
1
TRPA3
CCR2
Common Control Register 2
71h
6
0
BPCLK Frequency (MHz)
TRPA2
5
0
16.384
8.192
4.096
2.048
TRPA1
4
0
222 of 265
TRPA0
3
0
BPCS1
2
0
BPCS0
1
0
BPEN
0
0