DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 27

• Manufacturer Part Number: DS2156L+
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2156L+

• Function: Single-Chip Transceiver
• Interface: E1, J1, T1, TDM, UTOPIA II
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

3.2.2 Transmit Side
Signal Name:
Signal Description:
Signal Type:
This 5-bit wide bus is driven by the ATM layer to poll and select the appropriate UTOPIA port. UT-ADDR4 is the
MSB; UT-ADDR0 is the LSB.
Signal Name:
Signal Description:
Signal Type:
Active-low enable signal asserted by ATM layer during cycles when UT-DATAx contains valid cell data.
Signal Name:
Signal Description:
Signal Type:
Active-high signal asserted by ATM layer when UT-DATAx contains the first valid byte of the cell.
Signal Name:
Signal Description:
Signal Type:
Byte-wide true data driven from ATM layer to one of the selected ports. UT-DATA7 is the MSB; UT-DATA0 is
the LSB.
Signal Name:
Signal Description:
Signal Type:
This active-high UT-CLAV signal is asserted by the DS2156 if it has a cell space available to accommodate a
complete cell from the ATM layer to the polled port.
Signal Name:
Signal Description:
Signal Type:
This active-high signal is asserted by the DS2156 to indicate that the transmitter can accommodate two cells. UT-
2CLAV0 is driven in multiplexed bus with 1CLAV mode as well as direct status mode for port 0. The timing of
this signal follows as that of UT-CLAV. This bus is not tri-statable.
Signal Name:
Signal Description:
Signal Type:
Access to the data prior to the transmit formatter. Updated on the rising edge of TCLK. This output is normally
connected to TDATA.
Signal Name:
Signal Description:
Signal Type:
Transmit UTOPIA bus clock.
UT-ADDR0 to UT-ADDR4
Transmit UTOPIA Address
Input
UT-ENB
Transmit UTOPIA Enable
Input
UT-SOC
Transmit UTOPIA Start of Cell
Input
UT-DATA0 to UT-DATA7
Transmit UTOPIA Data Bus
Input
UT-CLAV
Transmit UTOPIA Cell Available
Output
UT-2CLAV
Transmit UTOPIA 2 Cells Available
Output
UT-UTDO
UTOPIA Transmit Data Output
Output
UT-CLK
Receive UTOPIA Clock
Input
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