DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 63

• Manufacturer Part Number: DS2156L+
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2156L+

• Function: Single-Chip Transceiver
• Interface: E1, J1, T1, TDM, UTOPIA II
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Table 9-A. E1 Sync/Resync Criteria
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Carrier-Loss (RCL) Alternate Criteria (RCLA). Defines the criteria for a receive carrier-loss
condition for both the framer and LIU.
Bits 1, 2/Unused, must be set to 0 for proper operation
Bit 3/Sa4 Bit Select (Sa4S). Set to 1 to have RLCLK pulse at the Sa4 bit position; set to 0 to force RLCLK low
during Sa4 bit position. See Section 34 for details.
Bit 4/Sa5 Bit Select (Sa5S). Set to 1 to have RLCLK pulse at the Sa5 bit position; set to 0 to force RLCLK low
during Sa5 bit position. See Section 34 for details.
Bit 5/Sa6 Bit Select (Sa6S). Set to 1 to have RLCLK pulse at the Sa6 bit position; set to 0 to force RLCLK low
during Sa6 bit position. See Section 34 for details.
Bit 6/Sa7 Bit Select (Sa7S). Set to 1 to have RLCLK pulse at the Sa7 bit position; set to 0 to force RLCLK low
during Sa7 bit position. See Section 34 for details.
Bit 7/Sa8 Bit Select (Sa8S). Set to 1 to have RLCLK pulse at the Sa8 bit position; set to 0 to force RLCLK low
during Sa8 bit position. See Section 34 for details.
MULTIFRAME
FRAME OR
LEVEL
CRC4
CAS
FAS
0 = RCL declared upon 255 consecutive 0s (125µs)
1 = RCL declared upon 2048 consecutive 0s (1ms)
Sa8S
7
0
FAS present in frame N and
N + 2; FAS not present in
frame N + 1
Two valid MF alignment
words found within 8ms
Valid MF alignment word
found and previous time slot
16 contains code other than
all 0s
Sa7S
E1RCR2
E1 Receive Control Register 2
34h
6
0
SYNC CRITERIA
Sa6S
5
0
Sa5S
4
0
63 of 265
Three consecutive incorrect
FAS received
Alternate: (E1RCR1.2 = 1) The
above criteria is met or three
consecutive incorrect bit 2 of
non-FAS received
915 or more CRC4 codewords
out of 1000 received in error
Two consecutive MF
alignment words received in
error
Sa4S
RESYNC CRITERIA
3
0
—
2
0
—
1
0
RCLA
4.2 and 4.3.2
ITU SPEC.
0
0
G.706
G.706
G.732
4.1.1
4.1.2
5.2
DS2156