AT32UC3A0128 Atmel Corporation, AT32UC3A0128 Datasheet - Page 392

• Manufacturer Part Number: AT32UC3A0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
Figure 27-26. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select.
27.6.7
27.6.7.1
Write2 controlling
Read1 controlling
NBS0, NBS1,
signal(NWE)
signal(NRD)
CLK_SMC
A0, A1
A[25:2]
D[15:0]
External Wait
Restriction
TDF_CYCLES = 5
Any access can be extended by an external device using the NWAIT input signal of the SMC.
The EXNW_MODE field of the MODE register on the corresponding chip select must be set to
either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00” (dis-
abled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal
delays the read or write operation in regards to the read or write controlling signal, depending on
the read and write modes of the corresponding chip select.
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold
cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be
used in Page Mode
(”Slow Clock Mode” on page
The NWAIT signal is assumed to be a response of the external device to the read/write
request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the
read or write controlling signal. The assertion of the NWAIT signal outside the expected
period has no impact on SMC behavior.
Read1 cycle
Read1 hold = 1
Read to Write
(”Asynchronous Page Mode” on page
Wait State
TDF_CYCLES = 5
398).
4 TDF WAIT STATES
400), or in Slow Clock Mode
Write2 setup = 1
(optimization disabled)
TDF_MODE=0
Write 2 cycle
AT32UC3A
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