AT32UC3A0128 Atmel Corporation, AT32UC3A0128 Datasheet - Page 428

• Manufacturer Part Number: AT32UC3A0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
•
Reset value is two cycles.
In the SDRAMC, only a CAS latency of one, two and three cycles is managed.
•
Reset value is 16 bits
0: Data bus width is 32 bits.
1: Data bus width is 16 bits.
•
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
•
Reset value is seven cycles.
This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is
between 0 and 15.
•
Reset value is three cycles.
This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles
is between 0 and 15.
•
Reset value is two cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of
cycles is between 0 and 15.
•
Reset value is five cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of
cycles is between 0 and 15.
•
Reset value is height cycles.
This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is
between 0 and 15.
CAS: CAS Latency
DBW: Data Bus Width
TWR: Write Recovery Delay
TRC: Row Cycle Delay
TRP: Row Precharge Delay
TRCD: Row to Column Delay
TRAS: Active to Precharge Delay
TXSR: Exit Self Refresh to Active Delay
0
0
1
1
CAS
0
1
0
1
CAS Latency (Cycles)
Reserved
1
2
3
AT32UC3A
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