AT32UC3A0128 Atmel Corporation, AT32UC3A0128 Datasheet - Page 583

• Manufacturer Part Number: AT32UC3A0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
• OVERFE: Overflow Interrupt Enable
Set by software (by setting the OVERFES bit) to enable the Overflow interrupt (OVERFI).
Clear by software (by setting the OVERFEC bit) to disable the Overflow interrupt (OVERFI).
• STALLEDE: STALLed Interrupt Enable
Set by software (by setting the STALLEDES bit) to enable the STALLed interrupt (STALLEDI).
Clear by software (by setting the STALLEDEC bit) to disable the STALLed interrupt (STALLEDI).
• CRCERRE: CRC Error Interrupt Enable
Set by software (by setting the CRCERRES bit) to enable the CRC Error interrupt (CRCERRI).
Clear by software (by setting the CRCERREC bit) to disable the CRC Error interrupt (CRCERRI).
• SHORTPACKETE: Short Packet Interrupt Enable
Set by software (by setting the SHORTPACKETES bit) to enable the Short Packet interrupt (SHORTPACKET).
Clear by software (by setting the SHORTPACKETEC bit) to disable the Short Packet interrupt (SHORTPACKET).
• NBUSYBKE: Number of Busy Banks Interrupt Enable
Set by software (by setting the NBUSYBKES bit) to enable the Number of Busy Banks interrupt (NBUSYBK).
Clear by software (by setting the NBUSYBKEC bit) to disable the Number of Busy Banks interrupt (NBUSYBK).
• KILLBK: Kill IN Bank
Set by software (by setting the KILLBKS bit) to kill the last written bank.
Cleared by hardware when the bank is killed.
Caution: The bank is really cleared when the “kill packet” procedure is accepted by the USB macro core. This bit is auto-
matically cleared after the end of the procedure:
The software shall wait for this bit to be cleared before trying to kill another packet.
Note that this kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent
on the USB line. If at least 2 banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming.
Indeed, in this case, the current bank is sent (IN transfer) while the last bank is killed.
• FIFOCON: FIFO Control
For control endpoints:
For IN endpoints:
For OUT endpoints:
– The bank is really cleared or the bank is sent (IN transfer): NBUSYBK is decremented.
– The bank is not cleared but sent (IN transfer): NBUSYBK is decremented.
– The bank is not cleared because it was empty.
The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints.
When read, their value is always 0.
Set by hardware when the current bank is free, at the same time as TXINI.
Clear by software (by setting the FIFOCONC bit) to send the FIFO data and to switch to the next bank.
Set by hardware when the current bank is full, at the same time as RXOUTI.
AT32UC3A
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