AT32UC3A0128 Atmel Corporation, AT32UC3A0128 Datasheet - Page 529

• Manufacturer Part Number: AT32UC3A0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
30.7.4
Figure 30-30. Example of DMA Chained List
USB DMA Channel X Registers
(Current Transfer Descriptor)
Next Descriptor Address
Memory Area
Data Buffer 1
Data Buffer 2
Data Buffer 3
HSB Address
USB DMA Operation
Control
Status
USB packets of any length may be transferred when required by the USB controller. These
transfers always feature sequential addressing. These two characteristics mean that in case of
high USB controller throughput, both HSB ports will benefit from “incrementing burst of unspeci-
fied length” since the average access latency of HSB slaves can then be reduced.
The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data
transfers and channel descriptor loading. A burst may last on the HSB busses for the duration of
a whole USB packet transfer, unless otherwise broken by the HSB arbitration or the HSB 1 kbyte
boundary crossing.
Packet data HSB bursts may be locked on a DMA buffer basis for drastic overall HSB bus band-
width performance boost with paged memories. This is because these memories row (or bank)
changes, which are very clock-cycle consuming, will then likely not occur or occur once instead
of dozens of times during a single big USB packet DMA transfer in case other HSB masters
address the memory. This means up to 128 words single cycle unbroken HSB bursts for bulk
pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints.
This maximal burst length is then controlled by the lowest programmed USB pipe/endpoint size
(PSIZE/EPSIZE) and DMA channel byte length (CH_BYTE_LENGTH).
The USB controller average throughput may be up to nearly 1.5 Mbyte/s. Its average access
latency decreases as burst length increases due to the 0 wait-state side effect of unchanged
pipe/endpoint. Word access allows reducing the HSB bandwidth required for the USB by 4 com-
pared to native byte access. If at least 0 wait-state word burst capability is also provided by the
other DMA HSB bus slaves, each of both DMA HSB busses need less than 1.1% bandwidth
allocation for full USB bandwidth usage at 33 MHz, and less than 0.6% at 66 MHz.
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
AT32UC3A
NULL
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