AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 132

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.23 PSC Clock Sources
12.24 Interrupts
132
AT90PWM81
According to the architecture of the PSC synchronization which build a “daisy-chain on the PSC run sig-
nal” between the three PSC, only the fault event (mode 7) which is able to “stop” the PSC through the
PRUN bits is transmitted along this daisy-chain.
A PSC which receive its Run signal from the previous PSC transmits its fault signal (if enabled) to this
previous PSC. So a slave PSC propagates its fault events when they are configured and enabled.
PSC must be able to generate high frequency with enhanced resolution.
Each PSC has two clock inputs:
Figure 12-42. Clock selection
PCLKSELn bit in PSC n Configuration register (PCNFn) is used to select the clock source.
PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the clock.
Table 12-10.
This section describes the specifics of the interrupt handling as performed in AT90PWM81.
PCLKSELn
0
0
0
0
1
1
1
1
• CLK PLL from the PLL
• CLK I/O
CLK
CLK
PLL
I/O
Output Clock versus Selection and Prescaler
PCLKSELn
PPREn1
0
0
1
1
0
0
1
1
1
0
CK
PPREn0
0
1
0
1
0
1
0
1
PRESCALER
CLK
CLKPSCn output
CLK I/O
CLK I/O / 4
CLK I/O / 32
CLK I/O / 256
CLK PLL
CLK PLL / 4
CLK PLL / 32
CLK PLL / 256
PSCn
PPREn1/0
7734P–AVR–08/10