AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 38

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.4
5.4.1
5.4.2
5.5
5.5.1
38
System Clock Prescaler
Register Description
AT90PWM81
Features
Switching Time
OSCCAL – Oscillator Calibration Register
The AT90PWM81 system clock can be divided by setting the Clock Prescaler Register – CLKPR. This
feature can be used to decrease power consumption when the requirement for processing power is low.
This can be used with all clock source options, and it will affect the clock frequency of the CPU and all
synchronous peripherals. clk
10 on page
When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in
the clock system and that no intermediate frequency is higher than neither the clock frequency corre-
sponding to the previous setting, nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may
be faster than the CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler –
even if it were readable, and the exact time it takes to switch from one clock division to another cannot be
exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous
clock period, and T2 is the period corresponding to the new prescaler setting.
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process
variations from the oscillator frequency. The factory-calibrated value is automatically written to this regis-
ter during chip reset, giving an oscillator frequency of 8.0 MHz at 25°C. The application software can
write this register to change the oscillator frequency. The oscillator can be calibrated to any frequency in
the range 7.6 - 8.4 MHz within ± 1% accuracy. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be
affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Other-
wise, the EEPROM or Flash write may fail.
The CAL7..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the
lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. Increment-
ing CAL7..0 by 1 will give a frequency increment of less than 0.5% in the frequency range 7.6 - 8.4 MHz.
Bit
Read/Write
Initial Value
39.
CAL7
R/W
7
CAL6
R/W
I/O
6
, clk
ADC
CAL5
R/W
, clk
5
Device Specific Calibration Value
CPU
, and clk
CAL4
R/W
4
FLASH
CAL3
R/W
3
are divided by a factor as shown in
CAL2
R/W
2
CAL1
R/W
1
CAL0
R/W
0
7734P–AVR–08/10
OSCCAL
Table 5-