AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 90

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.3.1
11.4
90
Counter Unit
AT90PWM81
External Clock Source
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clk
T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized
(sampled) signal is then passed through the edge detector.
block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the pos-
itive edge of the internal system clock (
system clock.
The edge detector generates one clk
edge it detects.
Figure 11-2.
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an
edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system
clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure cor-
rect sampling. The external clock must be guaranteed to have less than half the system clock frequency
(f
quency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crys-
tal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock
source is less than f
An external clock source can not be prescaled.
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
11-3
Figure 11-3.
ExtClk
shows a block diagram of the counter and its surroundings.
Tn
< f
clk
clk_I/O
I/O
TCNTnH (8-bit)
TEMP (8-bit)
/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum fre-
T1/T0 Pin Sampling
Counter Unit Block Diagram
TCNTn (16-bit Counter)
DATA BUS
clk_I/O
D
LE
Q
/2.5.
TCNTnL (8-bit)
(8-bit)
Synchronization
D
T1
Q
/clk
clk
T
0
Count
I/O
Clear
pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6)
). The latch is transparent in the high period of the internal
Control Logic
TOP
BOTTOM
TOVn
(Int.Req.)
clk
Tn
Figure 11-2
D
Clock Select
Q
( Ckio )
Detector
Edge
shows a functional equivalent
Edge Detector
Tn
7734P–AVR–08/10
T1
Tn_sync
(To Clock
Select Logic)
/clk
T0
Figure
). The