AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 173

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13.23.5
13.23.6
7734P–AVR–08/10
Output Compare RB Register – OCR0RBH and OCR0RBL
PSCR Configuration Register – PCNF0
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared
with the PSCR counter value. A match can be used to generate an Output Compare interrupt, or to gener-
ate a waveform output on the associated pin.
The Output Compare Registers RB contains also a 4-bit value that is used for the flank width modulation.
The Output Compare Registers are 12-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary
high byte register (TEMP). This temporary register is shared by all the other 16-bit registers.
• Bit 7 - PFIFTY0: PSCR Fifty
Writing this bit to one, set the PSCR in a fifty percent mode where only OCR0RBH/L and OCR0SBH/L
are used. They are duplicated in OCR0RAH/L and OCR0SAH/L during the update of OCR0RBH/L. This
feature is useful to perform fifty percent waveforms.
• Bit 6 - PALOCK0: PSCR Autolock
When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and the PSCR
Output Configuration PSOC0 can be written without disturbing the PSCR cycles. The update of the PSCR
internal registers will be done at the end of the PSCR cycle if the Output Compare Register RB has been
the last written.
When set, this bit prevails over LOCK (bit 5)
• Bit 5 – PLOCK0: PSCR Lock
When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2 and the
PSCR Output Configuration PSOC0 can be written without disturbing the PSCR cycles. The update of the
PSCR internal registers will be done if the LOCK bit is released to zero.
• Bit 4:3 – PMODE01: 0: PSCR Mode
Select the mode of PSC.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
7
PFIFTY0
R/W
0
7
OCR0RB[15:12]
OCR0RB[7:0]
W
0
6
W
0
6
PALOCK0 PLOCK0
R/W
0
5
W
0
5
R/W
0
0
4
PMODE01 PMODE00 POP0
R/W
0
4
W
3
R/W
0
3
OCR0RB[11:8]
W
0
2
R/W
0
2
W
0
1
PCLKSEL0 -
R/W
0
1
W
0
AT90PWM81
0
R/W
0
0
W
0
PCNF0
OCR0RBH
OCR0RBL
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