ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 105

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.11.6
10.11.7
8265B–AVR–09/10
TIMSK0 – Timer/Counter0 Interrupt Mask Register
TIFR0 – Timer/Counter0 Interrupt Flag Register
• Bits 7:2 – Res: Reserved Bits
These bits are reserved in the ATtiny87/167 and will always read as zero.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is exe-
cuted if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter0 Inter-
rupt Flag Register – TIFR0.
• Bits 7:2 – Res: Reserved Bits
These bits are reserved in the ATtiny87/167 and will always read as zero.
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and
the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a
logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Inter-
rupt Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Interrupt is
executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The TOV0 bit is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is
cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0A (Timer/Counter0
Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is
executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at
0x00.
Bit
(0x6E)
Read/Write
Initial Value
Bit
0x15 (0x35)
Read/Write
Initial Value
R
R
7
–
0
7
–
0
R
R
0
6
–
0
6
–
R
R
5
–
0
5
–
0
R
R
4
–
0
4
–
0
R
3
–
0
R
3
–
0
R
R
2
–
0
2
–
0
OCIE0A
OCF0A
R/W
R/W
1
0
1
0
TOIE0
TOV0
R/W
R/W
0
0
0
0
TIMSK0
TIFR0
105