ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 149

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14. USI – Universal Serial Interface
14.1
14.2
8265B–AVR–09/10
Features
Overview
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The Universal Serial Interface, or USI, provides the basic hardware resources needed for
serial communication. Combined with a minimum of control software, the USI allows signifi-
cantly higher transfer rates and uses less code space than solutions based on software only.
Interrupts are included to minimize the processor load.
A simplified block diagram of the USI is shown on
pins, refer to
and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in
the
Figure 14-1. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register is directly accessible via the data bus and contains the incoming
and outgoing data. The register has no buffering so the data must be read as quickly as possi-
ble to ensure that no data is lost. The USI Data Register is a serial shift register and the most
significant bit that is the output of the serial shift register is connected to one of two output pins
depending of the wire mode configuration.
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
“Register Description” on page
“Pin Configuration” on page
USIDR
USICR
USIDB
USISR
2
4-bit Counter
156.
3
2
1
0
3
2
1
0
D Q
LE
4. CPU accessible I/O Registers, including I/O bits
[1]
TIM0 COMP
0
1
Figure 14-1
Two-wire Clock
Control Unit
For the actual placement of I/O
CLOCK
HOLD
DO
DI/SDA
USCK/SCL
(Output only)
(Input/Open Drain)
(Input/Open Drain)
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