ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 65

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.3.5
8.3.6
8.3.7
8265B–AVR–09/10
PCIFR – Pin Change Interrupt Flag Register
PCMSK1 – Pin Change Mask Register 1
PCMSK0 – Pin Change Mask Register 0
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT[15:8] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT[15:8] pins are enabled individually by the PCMSK1 Register.
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT[7:0] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK0 Register.
• Bits 7:2 – Res: Reserved Bits
These bits are reserved bits in the ATtiny87/167 and will always read as zero.
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT[15:8] pin triggers an interrupt request, PCIF1 becomes
set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 7:0 – PCINT[15:8]: Pin Change Enable Mask 15:8
Each PCINT[15:8] bit selects whether pin change interrupt is enabled on the corresponding
I/O pin. If PCINT[15:8] is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled
on the corresponding I/O pin. If PCINT[15:8] is cleared, pin change interrupt on the corre-
sponding I/O pin is disabled.
Bit
0x1B (0x3B)
Read/Write
Initial Value
Bit
(0x6C)
Read/Write
Initial Value
Bit
(0x6B)
Read/Write
Initial Value
PCINT15
PCINT7
R/W
R/W
R
7
0
7
–
0
7
0
PCINT14
PCINT6
R/W
R/W
R
6
0
6
0
6
–
0
PCINT13
PCINT5
R/W
R/W
R
5
0
5
–
0
5
0
PCINT12
PCINT4
R/W
R/W
R
4
0
4
–
0
4
0
PCINT3
PCINT11
R/W
R/W
R
3
0
3
–
0
3
0
PCINT10
PCINT2
R/W
R/W
2
0
R
2
–
0
2
0
PCINT1
PCINT9
PCIF1
R/W
R/W
R/W
1
0
1
0
1
0
PCINT0
PCINT8
PCIF0
R/W
R/W
R/W
0
0
0
0
0
0
PCMSK0
PCMSK1
PCIFR
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