ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 183

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.6.3
15.6.4
8265B–AVR–09/10
LINENIR – LIN Enable Interrupt Register
LINERR – LIN Error Register
• Bit 0 – LRXOK: Receive Performed Interrupt
• Bits 7:4 – Reserved Bits
• Bit 3 – LENERR: Enable Error Interrupt
• Bit 2 – LENIDOK: Enable Identifier Interrupt
• Bit 1 – LENTXOK: Enable Transmit Performed Interrupt
• Bit 0 – LENRXOK: Enable Receive Performed Interrupt
• Bit 7 – LABORT: Abort Flag
Bit
(0xCA)
Read/Write
Initial Value
Bit
(0xCB)
Read/Write
Initial Value
LINENIR.
These bits are reserved for future use. For compatibility with future devices, they must be
written to zero when LINENIR is written.
– 0 = No Rx
– 1 = Rx Response complete.
– 0 = Error interrupt masked,
– 1 = Error interrupt enabled.
– 0 = Identifier interrupt masked,
– 1 = Identifier interrupt enabled.
– 0 = Transmit performed interrupt masked,
– 1 = Transmit performed interrupt enabled.
– 0 = Receive performed interrupt masked,
– 1 = Receive performed interrupt enabled.
– 0 = No warning,
– 1 = LIN abort command occurred.
This bit generates an interrupt if its respective enable bit - LENRXOK - is set in
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by reading LINDAT.
This bit is cleared when LERR bit in LINSIR is cleared.
LABORT
R
7
–
0
R
7
0
LTOERR
R
6
–
0
R
6
0
R
5
–
0
LOVERR
R
5
0
R
4
–
0
LFERR
R
4
0
LENERR
R/W
3
0
LSERR
R
3
0
LENIDOK
R/W
2
0
LPERR
R
2
0
LENTXOK
R/W
LCERR
1
0
R
1
0
LENRXOK
LBERR
R/W
0
0
R
0
0
LINENIR
LINERR
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