ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 92

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.6.1
10.6.2
10.7
92
Modes of Operation
ATtiny87/ATtiny167
Compare Output Function
Compare Output Mode and Waveform Generation
Figure 10-4. Compare Match Output Logic
The general I/O port function is overridden by the Output Compare (OC0A) from the Wave-
form Generator if either of the COM0A[1:0] bits are set. However, the OC0A pin direction
(input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The
Data Direction Register bit for the OC0A pin (DDR_OC0A) must be set as output before the
OC0A value is visible on the pin. The port override function is independent of the Waveform
Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0A state before the
output is enabled. Note that some COM0A[1:0] bit settings are reserved for certain modes of
operation.
The Waveform Generator uses the COM0A[1:0] bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM0A[1:0] = 0 tells the Waveform Generator that no
action on the OC0A Register is to be performed on the next compare match. For compare out-
put actions in the non-PWM modes refer to
refer to
A change of the COM0A[1:0] bits state will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the FOC0A strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM0[1:0]) and Compare
Output mode (COM0A[1:0]) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM0A[1:0] bits control
whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
For non-PWM modes the COM0A[1:0] bits control whether the output should be set, cleared,
or toggled at a compare match
Table 10-2 on page
See ”Register Description” on page 100.
COMnx1
COMnx0
FOCnx
clk
I/O
Waveform
Generator
101, and for phase correct PWM refer to
(See ”Compare Match Output Unit” on page
D
D
D
PORT
DDR
OCnx
Table 10-1 on page
Q
Q
Q
1
0
101. For fast PWM mode,
Table 10-3 on page
OCnx
91.).
Pin
8265B–AVR–09/10
101.