ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 205

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.11 Register Description
17.11.1
8265B–AVR–09/10
ADMUX – ADC Multiplexer Selection Register
• Bits 7:6 – REFS[1:0]: Voltage Reference Selection Bits
These bits and AREFEN bit from the Analog Miscellaneous Control Register (AMISCR) select
the voltage reference for the ADC, as shown in
conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA
register is set). Whenever these bits are changed, the next conversion will take 25 ADC clock
cycles. If active channels are used, using AVCC or an external AREF higher than (AV
is not recommended, as this will affect ADC accuracy. The internal voltage reference options
may not be used if an external voltage is being applied to the AREF pin.
Table 17-4.
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Regis-
ter. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted.
Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any
ongoing conversions. For a complete description of this bit, see
Data Register” on page
• Bits 4:0 – MUX[4:0]: Analog Channel and Gain Selection Bits
These bits select which combination of analog inputs are connected to the ADC. In case of dif-
ferential input, gain selection is also made with these bits. Refer to
these bits are changed during a conversion, the change will not go into effect until this
conversion is complete (ADIF in ADCSRA register is set).
Bit
(0x7C)
Read/Write
Initial Value
REFS1
X
X
0
1
REFS0
Voltage Reference Selections for ADC
REFS1
0
0
1
1
R/W
7
0
AREFEN Voltage Reference (V
REFS0
208.
R/W
0
6
0
1
0
0
ADLAR
AV
External Voltage Reference at AREF pin (AREF ≥ 2.0V)
Internal 1.1V Voltage Reference
Internal 2.56V Voltage Reference
R/W
5
0
CC
used as Voltage Reference, diconnected from AREF pin
MUX4
R/W
4
0
Table
MUX3
R/W
3
0
REF
17-4. If these bits are changed during a
) Selection
MUX2
R/W
2
0
“ADCL and ADCH – ADC
MUX1
R/W
Table 17-5
1
0
MUX0
R/W
0
0
for details. If
ADMUX
CC
- 1V)
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