ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 118

• Manufacturer Part Number: ATxmega64A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A1

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.4
11.5
11.6
8077H–AVR–12/09
Window Mode Operation
Watchdog Timer clock
Configuration Protection and Lock
In window mode operation the WDT uses two different timeout periods, a "closed" window time-
out period (TO
defines a duration from 8 ms to 8s where the WDT cannot be reset: if the WDT is reset in this
period the WDT will issue a system reset. The normal WDT timeout period, which is also 8 ms to
8s, defines the duration of the "open" period, in which the WDT can (and should) be reset. The
open period will always follow the closed period, so the total duration of the timeout period is the
sum of the closed window and the open window timeout periods. The default closed window tim-
eout period is controlled by fuses. The window mode operation is illustrated in
Figure 11-2. Window mode operation.
The WDT is clocked from the 1 kHz output from the internal 32 kHz Ultra Low Power (ULP) oscil-
lator. Due to the ultra low power design, the oscillator is not very accurate so the exact timeout
period may vary from device to device. When designing software which uses the WDT, this
device-to-device variation must be kept in mind to ensure that the timeout periods used are valid
for all devices. For more information on the ULP oscillator accuracy, consult the device data
sheet.
The WDT is designed with two security mechanisms to avoid unintentional changes of the WDT
settings.
The first mechanism is the Configuration Change Protection mechanism, employing a timed
write procedure for changing the WDT control registers. In addition, for the new configuration to
be written to the control registers, the register’s Change Enable bit must be written at the same
time.
The second mechanism is to lock the configuration by setting the WDT lock fuse. When this fuse
is set, the Watchdog Time Control Register can not be changed, hence the WDT can not be dis-
abled from software. After system reset the WDT will resume at configured operation. When the
WDT lock fuse is programmed the window mode timeout period cannot be changed, but the win-
dow mode itself can still be enabled or disabled.
TO
TO
WDTW
WDT
WDTW
= 8
= 8
WDT Count
) and the normal timeout period (TO
5
10
15
TO
WDTW
20
TO
25
WDT
WDT
). The closed window timeout period
30
Timely WDT
Reset
35
Early WDT Reset
t [ms]
System Reset
XMEGA A
Figure
11-2.
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