ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 325

• Manufacturer Part Number: ATxmega64A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A1

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.10.7.1
26.10.7.2
26.10.8
26.10.8.1
26.10.8.2
26.10.9
8077H–AVR–12/09
CH0DATAL – DAC Channel 0 Data Register Low
CH1DATAH – DAC Channel 1 Data Register High
Right-adjusted
Left-adjusted
Right-adjusted
Left-adjusted
• Bits 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 3:0 - CHDATA[11:8]: DAC Conversion Data Register Channel 0, 4 MSB
These bits are the 4 MSB of the 12-bit value to convert to channel 0 in right-adjusted mode.
• Bits 7:0 - CHDATA[11:4]: DAC Conversion Data Register Channel 0, 8 MSB
These bits are the 8 MSB of the 12-bit value to convert to channel 0 in left-adjusted mode.
• Bits 7:0 - CHDATA[7:0]: DAC Conversion Data Register Channel 0, 8 LSB
These bits are the 8 LSB of the 12-bit value to convert to channel 0 in right-adjusted mode.
• Bits 7:4 - CHDATA[3:0]: DAC Conversion Data Register Channel 0, 4 LSB
These bits are the 4 LSB of the 12-bit value to convert to channel 0 in left-adjusted mode.
• Bits 3:0 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Bit
+0x18
Read/Write
Read/Write
Initial Value
Initial Value
Bit
+0x1B
Read/Write
Read/Write
Initial Value
Initial Value
7
R/W
R/W
R/W
R
0
0
7
0
0
-
6
R/W
R/W
R/W
R
0
0
6
0
0
-
CHDATA[3:0]
5
R/W
R/W
R/W
R
0
0
5
0
0
-
4
R/W
R/W
R/W
0
0
4
R
0
0
CHDATA[11:4]
-
CHDATA[7:0]
3
R/W
R/W
R/W
R
0
0
3
0
0
-
2
R/W
R/W
R/W
R
0
0
2
0
0
-
CHDATA[11:8]
XMEGA A
1
R/W
R/W
R/W
R
0
0
1
0
0
-
0
R/W
R/W
R/W
R
0
0
0
0
0
-
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