ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 59

• Manufacturer Part Number: ATxmega64A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A1

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8077H–AVR–12/09
Table 5-8.
Table 5-9.
TRGSRC offset value
TRIGSRC base value
+0x00
+0x01
+0x02
0xAA
0xAB
0xAE
0x4A
0x4B
0x4E
0x6A
0x6B
0x6E
0x8A
0x8B
0x8E
0xA0
0xA6
0x00
0x01
0x10
0x15
0x20
0x25
0x40
0x46
0x60
0x66
0x80
0x86
DMA Trigger Sources, base value for all modules and peripherals
DMA Trigger sources, offset values for Event System triggers
Group Configuration
Group Configuration
USARTC0
USARTC1
USARTD0
USARTD1
USARTE0
USARTE1
USARTF0
USARTF1
ADCA
DACA
ADCB
DACB
TCC0
TCC1
TCD0
TCD1
TCE0
TCE1
TCF0
TCF1
SPIC
SPID
SPIE
SPIF
OFF
SYS
CH0
CH1
CH2
Description
Software triggers only
System DMA triggers base value
ADCA DMA triggers base value
DACA DMA trigger bas
ADCB DMA triggers base value
DACB DMA triggers base value
Timer/Counter C0 DMA triggers base value
Timer/Counter C1 triggers base value
SPI C DMA triggers value
USART C0 DMA triggers base value
USART C1 DMA triggers base value
Timer/Counter D0 DMA triggers base value
Timer/Counter D1 triggers base value
SPI D DMA triggers value
USART D0 DMA triggers base value
USART D1 DMA triggers base value
Timer/Counter E0 DMA triggers base value
Timer/Counter E1 triggers base value
SPI E DMA triggers value
USART E0 DMA triggers base value
USART E1 DMA triggers base value
Timer/Counter F0 DMA triggers base value
Timer/Counter F1 triggers base value
SPI F DMA trigger value
USART F0 DMA triggers base value
USART F1 DMA triggers base value
Description
Event Channel 0
Event Channel 1
Event Channel 2
XMEGA A
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