ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 241

• Manufacturer Part Number: ATxmega64A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A1

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.4.1
21.4.2
21.5
21.6
21.6.1
8077H–AVR–12/09
USART Initialization
Data Transmission - The USART Transmitter
Parity Bit Calculation
SPI Frame Formats
Sending Frames
Table 1.
Even or odd parity can be selected for error checking. If even parity is selected, the parity bit is
set to one if the number of data bits that is one is odd (making the total number of ones even). If
odd parity is selected, the parity bit is set to one if the number of data bits that is one is even
(making the total number of ones odd).
The serial frame in SPI mode is defined to be one character of 8 data bits. The USART in Master
SPI mode has two valid frame formats:
When a complete frame of 8 bits is transmitted, a new frame can directly follow it, or the commu-
nication line returns to idle (high) state.
USART initialization should use the following sequence:
For interrupt driven USART operation, global interrupts should be disabled during the
initialization.
Before doing a re-initialization with changed baud rate or frame format, be sure that there are no
ongoing transmissions during the period the registers are changed. The transit and receive com-
plete interrupt flags can be used to check that the Transmitter has completed all transfers, and
that there are no unread data in the receive buffer.
When the Transmitter has been enabled, the normal port operation of the TxD pin is overridden
by the USART and given the function as the Transmitter's serial output. The direction of the pin
must be set as output using the Direction register in the corresponding port. For details on port
pin control refer to
A data transmission is initiated by loading the transmit buffer (DATA) with the data to be sent.
The data in the transmit buffer is moved to the Shift Register when the Shift Register is empty
and ready to send a new frame. The Shift Register is loaded if it is in idle state (no ongoing
St
(n)
P
Sp
IDLE
• 8-bit data with MSB first
• 8-bit data with LSB first
1. Set the TxD pin value high, and optionally the XCK pin low.
2. Set the TxD and optionally the XCK pin as output.
3. Set the baud rate and frame format.
4. Set mode of operation (enables the XCK pin output in synchronous mode).
5. Enable the Transmitter or the Receiver depending on the usage.
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxD or TxD). The IDLE state is always high.
”I/O Ports” on page
129.
XMEGA A
241